In semiconductor technology, the efficient manufacture of MOS transistors is essential. Particularly for RF applications, the demand on the quality of transistors increases.
U.S. Pat. No. 5,828,104 discloses a MOS semiconductor device containing a MOSFET with an asymmetric LDD structure, which has in a semiconductor substrate a first heavily doped region, a lightly doped region formed adjacent to the first heavily doped region, and a second heavily doped region formed apart from the first lightly doped region. The first heavily doped region and the lightly doped region act as a drain region of the MOSFET, and the second heavily doped region acts as a source region thereof. A gate electrode composed of a plurality of parts is positioned over a channel region. At least one of the parts has a drain-side end, which is positioned over the lightly doped region, and a source-side end that is positioned over the channel region not to extend to the second heavily doped region.
However, conventional transistor manufacture procedures may fail when the dimensions become smaller and smaller.